| No. | Claims |
|---|
| 1 | A semiconductor device comprising:
a semiconductor body[308] having a top surface[316] and laterally opposite sidewalls formed on a substrate[102];
a gate dielectric[206] formed on said top surface[316] of said semiconductor body[308] and on said laterally opposite sidewalls[310] of said semiconductor body[308];
a gate electrode[110] formed on said gate dielectric[206] on said top surface[316] of said semiconductor body[308] and adjacent to said gate dielectric[206] on said laterally opposite sidewalls[310] of said semiconductor body[308];
and a film[360] formed adjacent to said semiconductor body[308]
wherein said film[360] produces a stress in said semiconductor body[308]. |
| 9 | A tri-gate transistor[300] comprising:
a single crystalline silicon body[106] formed on insulating substrate, said silicon body[106] having a top surface opposite a bottom surface[318] and a first and second laterally opposite sidewalls;
a gate dielectric[206] formed on said top surface[316] of said semiconductor body[308] and on said first and second laterally opposite sidewalls of said semiconductor body[308];
a gate electrode[110] formed on said gate dielectric[206] and on said top surface[316] of said silicon body[106] and adjacent to said gate dielectric[206] on said first and second laterally opposite sidewalls of said silicon body[106];
a pair of source/drain regions formed in said silicon body[106] on opposite sides of said gate electrode[110];
and a stress induced film formed around said silicon body[106] and said gate electrode[110], said film providing stress in the channel region[350] of said device[200]. |
| 17 | A method of forming a semiconductor device comprising:
forming a semiconductor body[308] having a top surface[316] and laterally opposite sidewalls on a insulating substrate[502];
forming a gate dielectric[206] on said top surface[316] of said semiconductor body[308] and on said laterally opposite sidewalls[310] of said semiconductor body[308];
forming a gate electrode[110] on said gate dielectric[206] and adjacent to said gate dielectric[206] on said laterally opposite sidewalls[310] of said semiconductor body[308];
and forming a thin film[360] adjacent to said semiconductor body[308]
wherein said thin film[360] produces a stress in said semiconductor body[308]. |
| 24 | A method of forming nonplanar transistor comprising:
patterning a monocrystalline silicon film formed on an insulating substrate[502] into a silicon body[106] having a top surface opposite a bottom surface[318] formed on said insulating film[506], and a first and second laterally opposite sidewalls;
forming a gate dielectric layer[108] on said top surface[316] of said silicon body[106] and on said sidewalls[310] of said silicon body[106];
depositing a gate material over said silicon body[106] and over said insulating substrate[502];
patterning said gate material to form a gate electrode[110] on said gate dielectric layer[108] on said top surface[316] of said silicon body[106] in adjacent to said gate dielectric[206] on said sidewalls[310] of said silicon body[106], said gate electrode[110] having laterally opposite sidewalls which run perpendicular to said laterally opposite sidewalls[310] of said silicon body[106];
forming a pair of source/drains regions in said silicon body[106] on opposite sides of said laterally opposite sidewalls[310] of said gate electrode[110],
wherein the region[330] between said source/drain regions in said silicon body[106] forms a channel region[350];
removing a portion[322] of said insulating substrate[502] from underneath a portion of channel region[350] of said silicon body[106] and beneath a portion[322] of said source and drain regions of said silicon body[106];
and forming a film[360] having a stress therein beneath said exposed portion of said silicon body[106] beneath said gate electrode[110] and beneath said exposed portion of said source and drain regions beneath said gate electrode[110]. |